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Intel unveils new chip design to challenge AMD

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yet another 'unpaid' announcement....









The Associated Press

Tuesday, August 19, 2008; 5:33 PM

SAN FRANCISCO -- Intel Corp. cracked the lid Tuesday on a new chip design that is at once a big challenge to smaller rival Advanced Micro Devices Inc. and an admission that AMD nailed a key design feature before it slipped into a severe financial slump.


Intel, the world's largest computer chip maker, showed off the new blueprint, known as a microarchitecture, for its chips at a developers conference in San Francisco.


Though some of the details were already known, the design's formal unveiling represented another demonstration of Intel's advantage over AMD in cranking out new chip designs once every two years, a factor that helped send AMD's stock price down 5 percent in an overall down day for technology shares.




The details of Intel's microprocessor architecture are always highly technical. But they're also closely watched because of the ubiquity of Intel's chips in personal computers and corporate servers.

One of the most significant changes was already known. Intel now plans to build a part called an integrated memory controller _ which moves information between the microprocessor and the computer's memory _ directly into the processor itself.




Because of that and other tweaks, Intel said its new design, which is code-named Nehalem, will triple the speed at which data can be written to memory or read back, compared to previous generations. Intel says Nehalem also will have nearly double the 3-D animation capabilities as past chips, and better utilize the multiple "cores," or processing engines, on each chip.


Chip makers are adding multiple cores to their chips, essentially jamming many separate processors onto the same slice of silicon, to make sure they're able to continue ramping up performance without running into overheating problems.


Intel said four-core Nehalem chips, which are due to be in production by the end of 2008 and will first target servers and desktop computers and later laptops, have the ability to turn individual cores on and off and can be programmed to boost the speed of active cores when the workload ramps up.

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Hey - good link.


Intel now plans to build a part called an integrated memory controller _ which moves information between the microprocessor and the computer's memory _ directly into the processor itself.




How does this differ from cache?

We have level 1 cache (sits outside the cpu) and level 2 cache (which sits inside the cpu). L3 cache sits between the L2 cache and main memory.

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I would think that it is increased thoroughput so that you do not need cache which sort of is like a reserve that fills up when demand is low to try and help out when demand increases. That is slower than having a direct infrastructure that can handle full load requirements. Just a guess on my part, but that is what I get out of reading that.

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21.08.2008 16:19

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IDF: turbo mode for Nehalem


In his keynote speech at Intel's developer forum, in addition to setting out time scales and giving some initial details, Pat Gelsinger, head of Intel's Digital Enterprise Group, also provided a few benchmark results for Intel's forthcoming processors. He also talked about a previously unpublished feature of the next generation of core processors – codename Nehalem, a feature previously known as burn-in mode or Foxton – for Itanium. Now known as "turbo mode", Intel's Nehalem processors will, in moderation, support overclocking. The processor's numerous thermal cut-outs ensure that it automatically underclocks if it overheats, thus ensuring that no damage can occur. The processor will be able to up its clock speed to a maximum of one class higher, i.e. to the speed of the next fastest processor.

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